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SKY55951-11
Electronics Part Number
SKY55951-11-WXManufacturer
onsemi
SKY55951-11
Description
SPDT RF Switch Operating from 2.4 to 8.3 GHz for Wideband Signal Path SelectionInventory
731 Pcs New Original In Stock
RF front end, 1.164-1.606GHz, 4G/5G, 20-MCM.
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Minimum 1
Minimum 1
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Technical Specifications
Category
Transistors, FETs, MOSFETs, FET, MOSFET Arrays
Manufacturer
onsemi
Packaging
Cut Tape (CT) & Digi-Reel®
Operating Temperature
-55°C ~ 150°C (TJ)
Mounting Type
Surface Mount
Package / Case
8-PowerWDFN
Series
PowerTrench®
Base Product Number
FDPC8
Product Status
Active
Technology
MOSFET (Metal Oxide)
Power - Max
800mW (Ta), 900mW (Ta)
Configuration
2 N-Channel (Dual) Asymmetrical
Supplier Device Package
Powerclip-33
Drain to Source Voltage (Vdss)
25V
Input Capacitance (Ciss) (Max) @ Vds
1240pF @ 13V, 4335pF @ 13V
Current - Continuous Drain (Id) @ 25°C
13A (Ta), 20A (Tc), 27A (Ta), 60A (Tc)
Rds On (Max) @ Id, Vgs
6mOhm @ 13A, 10V, 1.8mOhm @ 27A, 10V
Vgs(th) (Max) @ Id
2.2V @ 250µA, 2.2V @ 1mA
Gate Charge (Qg) (Max) @ Vgs
19nC @ 10V, 64nC @ 10V
FET Feature
-
Data Sheet Document (D)
Datasheets
Download FDPC8011S Product Specification (PDF)
HTML Datasheet
FDPC8011S-DG
Environmental & Export Classification
RoHS Status
ROHS3 Compliant
Moisture Sensitivity Level (MSL)
1 (Unlimited)
REACH Status
REACH Unaffected
ECCN
EAR99
HTSUS
8541.29.0095
Additional Information
Other Names
FDPC8011SFSDKR FDPC8011SFSTR 488-FDPC8011SDKR ONSONSFDPC8011S 488-FDPC8011SCT 488-FDPC8011STR 2156-FDPC8011S-OS FDPC8011SFSCT
Standard Package
3,000
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Frequently Asked Questions (FAQ)
When designing in the FDPC8011S for a dual N-channel MOSFET buck converter, how do the asymmetrical
The FDPC8011S features asymmetrical 6mΩ (@13A) and 1.8mΩ (@27A) Rds(on) values, indicating the two MOSFETs are optimized for different roles—typically one for high-side switching and one for synchronous rectification. Unequal on-resistances mean the low-side MOSFET (lower Rds(on)) will conduct higher pulsed currents with less loss, but mismatched conduction losses can cause thermal imbalance if both are placed close on the PCB without proper copper zoning. To mitigate risk, design with individual thermal pads and separate current paths, and validate under maximum load conditions to avoid localized overheating. Avoid parallel operation unless both channels are driven independently and thermally monitored.
Can the FDPC8011S replace the Infineon BSC023N04LS6 in a 24V motor drive while maintaining similar e
While both the FDPC8011S and BSC023N04LS6 are dual N-channel MOSFETs rated above 20V, the FDPC8011S has a lower Vds(max) at 25V compared to the BSC023N04LS6’s 40V, introducing a risk of avalanche breakdown during motor inductive kickback in 24V systems. Additionally, the FDPC8011S has higher Rds(on) (6mΩ vs. 2.3mΩ typical) at 10V Vgs, leading to increased conduction losses. If replacing, ensure strict control of inductive transients via freewheeling diodes or snubbers, validate gate drive alignment (Vgs(th) is comparable at ~2.2V), and increase PCB copper for heatsinking to compensate for lower efficiency. Not recommended for high-dynamic loads without derating.
What are the thermal design risks when operating the FDPC8011S near its maximum junction temperature
Operating the FDPC8011S near 150°C TJ in a sealed enclosure risks exceeding safe operating area (SOA) limits due to reduced heat dissipation. With a power dissipation rating of only 800mW (Ta), passive convection cooling is insufficient under sustained load. The Powerclip-33 package relies heavily on PCB-based thermal conduction through exposed pads—insufficient copper area or lack of thermal vias will accelerate thermal runaway. To reduce risk, use at least 2oz copper, implement 4–6 thermal vias under each MOSFET, and consider derating Id by 30–40% in ambient temperatures above 70°C. Monitor temperature during burn-in testing to validate long-term reliability.
How does the high total gate charge (64nC max) of the FDPC8011S affect switching losses and driver s
The FDPC8011S has a maximum Qg of 64nC at 10V, which significantly increases switching losses at frequencies above 100kHz. Driving this gate charge requires a capable driver (e.g., TC4427 or MIC5018) that can source/sink >2A peak current to minimize transition time and avoid shoot-through. In power-sensitive designs, using a resistor larger than 4.7Ω in the gate path can lead to excessive rise/fall times and thermal stress. To optimize efficiency, simulate switching behavior in your layout, minimize gate loop inductance, and consider active Miller clamping if Vgs ringing is observed. For apps above 200kHz, evaluate lower-Qg alternatives like the Nexperia BUK9Y8R7-20E.
Is the FDPC8011S susceptible to gate oxide damage during assembly, and what precautions should be ta
Although the FDPC8011S has an MSL 1 (unlimited) rating, indicating no moisture sensitivity during storage, the Powerclip-33’s small PowerWDFN footprint and gate oxides remain vulnerable to ESD and thermal shock during reflow. The 2.2V Vgs(th) suggests low-threshold operation, increasing risk of unintended turn-on from noise or leakage during soldering. Always use ESD-safe handling (wrist straps, grounded tools), control peak reflow temperature as per manufacturer profiles, and avoid liquid flux residues near gate pads. Verify post-soldering with resistance checks between Vgs nodes and ensure no static charge buildup during automated pick-and-place assembly to prevent latent gate failure.
When designing in the FDPC8011S for a dual N-channel MOSFET buck converter, how do the asymmetrical
The FDPC8011S features asymmetrical 6mΩ (@13A) and 1.8mΩ (@27A) Rds(on) values, indicating the two MOSFETs are optimized for different roles—typically one for high-side switching and one for synchronous rectification. Unequal on-resistances mean the low-side MOSFET (lower Rds(on)) will conduct higher pulsed currents with less loss, but mismatched conduction losses can cause thermal imbalance if both are placed close on the PCB without proper copper zoning. To mitigate risk, design with individual thermal pads and separate current paths, and validate under maximum load conditions to avoid localized overheating. Avoid parallel operation unless both channels are driven independently and thermally monitored.
Can the FDPC8011S replace the Infineon BSC023N04LS6 in a 24V motor drive while maintaining similar e
While both the FDPC8011S and BSC023N04LS6 are dual N-channel MOSFETs rated above 20V, the FDPC8011S has a lower Vds(max) at 25V compared to the BSC023N04LS6’s 40V, introducing a risk of avalanche breakdown during motor inductive kickback in 24V systems. Additionally, the FDPC8011S has higher Rds(on) (6mΩ vs. 2.3mΩ typical) at 10V Vgs, leading to increased conduction losses. If replacing, ensure strict control of inductive transients via freewheeling diodes or snubbers, validate gate drive alignment (Vgs(th) is comparable at ~2.2V), and increase PCB copper for heatsinking to compensate for lower efficiency. Not recommended for high-dynamic loads without derating.
What are the thermal design risks when operating the FDPC8011S near its maximum junction temperature
Operating the FDPC8011S near 150°C TJ in a sealed enclosure risks exceeding safe operating area (SOA) limits due to reduced heat dissipation. With a power dissipation rating of only 800mW (Ta), passive convection cooling is insufficient under sustained load. The Powerclip-33 package relies heavily on PCB-based thermal conduction through exposed pads—insufficient copper area or lack of thermal vias will accelerate thermal runaway. To reduce risk, use at least 2oz copper, implement 4–6 thermal vias under each MOSFET, and consider derating Id by 30–40% in ambient temperatures above 70°C. Monitor temperature during burn-in testing to validate long-term reliability.
How does the high total gate charge (64nC max) of the FDPC8011S affect switching losses and driver s
The FDPC8011S has a maximum Qg of 64nC at 10V, which significantly increases switching losses at frequencies above 100kHz. Driving this gate charge requires a capable driver (e.g., TC4427 or MIC5018) that can source/sink >2A peak current to minimize transition time and avoid shoot-through. In power-sensitive designs, using a resistor larger than 4.7Ω in the gate path can lead to excessive rise/fall times and thermal stress. To optimize efficiency, simulate switching behavior in your layout, minimize gate loop inductance, and consider active Miller clamping if Vgs ringing is observed. For apps above 200kHz, evaluate lower-Qg alternatives like the Nexperia BUK9Y8R7-20E.
Is the FDPC8011S susceptible to gate oxide damage during assembly, and what precautions should be ta
Although the FDPC8011S has an MSL 1 (unlimited) rating, indicating no moisture sensitivity during storage, the Powerclip-33’s small PowerWDFN footprint and gate oxides remain vulnerable to ESD and thermal shock during reflow. The 2.2V Vgs(th) suggests low-threshold operation, increasing risk of unintended turn-on from noise or leakage during soldering. Always use ESD-safe handling (wrist straps, grounded tools), control peak reflow temperature as per manufacturer profiles, and avoid liquid flux residues near gate pads. Verify post-soldering with resistance checks between Vgs nodes and ensure no static charge buildup during automated pick-and-place assembly to prevent latent gate failure.
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Sep 15 2026
