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RLS302-201M
Electronics Part Number
RLS302-201M-WXManufacturer
Broadcom
RLS302-201M
Description
200V 3kA Through-Hole Glass Discharge Tube, ±20%, RoHSInventory
585 Pcs New Original In Stock
-
Quantity
Minimum 1
Minimum 1
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Basic cost: USD 70.00
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Technical Specifications
Category
Optoisolators, Logic Output Optoisolators
Manufacturer
Broadcom
Packaging
Tape & Reel (TR)
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SMD, Gull Wing
Series
-
Base Product Number
HCPL-7723
Product Status
Active
Number of Channels
1
Output Type
Push-Pull, Totem Pole
Voltage - Isolation
3750Vrms
Voltage - Supply
4.5V ~ 5.5V
Input Type
Logic
Supplier Device Package
8-DIP Gull Wing
Voltage - Forward (Vf) (Typ)
-
Current - DC Forward (If) (Max)
-
Data Rate
50MBd
Common Mode Transient Immunity (Min)
10kV/µs
Current - Output / Channel
10 mA
Propagation Delay tpLH / tpHL (Max)
22ns, 22ns
Rise / Fall Time (Typ)
8ns, 6ns
Inputs - Side 1/Side 2
1/0
Data Sheet Document (D)
Datasheets
Download HCPL-7723-560E Product Specification (PDF)
HTML Datasheet
HCPL-7723-560E-DG
Environmental & Export Classification
RoHS Status
ROHS3 Compliant
Moisture Sensitivity Level (MSL)
1 (Unlimited)
REACH Status
REACH Unaffected
ECCN
EAR99
HTSUS
8541.49.8000
Additional Information
Standard Package
1,000
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Frequently Asked Questions (FAQ)
Can I drop-in replace a TI ISO7723DR in a 3.3 V-logic, 50 Mbps fieldbus with the Broadcom HCPL-7723-
No—HCPL-7723-560E is internally biased for 4.5–5.5 V on both sides; the TI part runs down to 2.25 V. Insert a 74LVC125 buffer on the input side or choose a 3.3-V opto such as ACPL-M61L if you want a one-to-one swap; otherwise the HCPL-7723-560E will not meet VIH at 3.3 V and data errors will appear around 30–40 MHz.
Will the HCPL-7723-560E survive a 45 kV EFT burst on the cable when its CMTI is only 10 kV/µs?
The 10 kV/µs CMTI rating guarantees signal integrity, not survival isolation; the HCPL-7723-560E is tested to 3750 Vrms for 60 s, so it can block the energy, but add a 100 pF Y-cap and 15 Ω series resistor on the PCB side to slow the dV/dt below 10 kV/µs and keep the opto’s output glitch-free during 5 ns EFT edges.
If I run the HCPL-7723-560E at 85 °C on a 24 h turbine controller, what derating should I apply to t
Keep load current ≤ 4 mA (40 % of 10 mA) and VCC at 4.5 V. This drops internal power to 18 mW, pulling junction rise below 10 °C above ambient and shifting the intrinsic failure rate from 20 FIT to <0.7 FIT per Telcordia; the 5 mA drive is still enough for 15 pF CMOS inputs at 50 Mbps.
Can I parallel two HCPL-7723-560E devices to get 20 mA sinking for a 3.3 V RS-422 driver, and will s
Yes for current, no for clean timing—tp skew between two units is ±6 ns max. Star-ground the outputs, add a 22 Ω common series resistor, then feed both inputs from a single LVDS receiver; the RC slows rise/fall to 4 ns, masking the skew and preventing 6 ns runt pulses on the differential line while still meeting 50 Mbps.
When swapping from Avago HCPL-7723 (old DIP-8 thru-hole) to HCPL-7723-560E gull-wing SMD during rewo
Use a 0.125 mm thick stencil with 80 % area aperture for pads 1, 4, 5, 8 (isolation barrier pins) and 90 % for signal pins; this deposits 120 µm paste that reflows to 70 µm standoff, giving enough compliance to absorb 13 ppm/°C difference between FR-4 and the HCPL-7723-560E’s epoxy compound across 1000 -40→85 °C cycles without corner crack failures.
Can I drop-in replace a TI ISO7723DR in a 3.3 V-logic, 50 Mbps fieldbus with the Broadcom HCPL-7723-
No—HCPL-7723-560E is internally biased for 4.5–5.5 V on both sides; the TI part runs down to 2.25 V. Insert a 74LVC125 buffer on the input side or choose a 3.3-V opto such as ACPL-M61L if you want a one-to-one swap; otherwise the HCPL-7723-560E will not meet VIH at 3.3 V and data errors will appear around 30–40 MHz.
Will the HCPL-7723-560E survive a 45 kV EFT burst on the cable when its CMTI is only 10 kV/µs?
The 10 kV/µs CMTI rating guarantees signal integrity, not survival isolation; the HCPL-7723-560E is tested to 3750 Vrms for 60 s, so it can block the energy, but add a 100 pF Y-cap and 15 Ω series resistor on the PCB side to slow the dV/dt below 10 kV/µs and keep the opto’s output glitch-free during 5 ns EFT edges.
If I run the HCPL-7723-560E at 85 °C on a 24 h turbine controller, what derating should I apply to t
Keep load current ≤ 4 mA (40 % of 10 mA) and VCC at 4.5 V. This drops internal power to 18 mW, pulling junction rise below 10 °C above ambient and shifting the intrinsic failure rate from 20 FIT to <0.7 FIT per Telcordia; the 5 mA drive is still enough for 15 pF CMOS inputs at 50 Mbps.
Can I parallel two HCPL-7723-560E devices to get 20 mA sinking for a 3.3 V RS-422 driver, and will s
Yes for current, no for clean timing—tp skew between two units is ±6 ns max. Star-ground the outputs, add a 22 Ω common series resistor, then feed both inputs from a single LVDS receiver; the RC slows rise/fall to 4 ns, masking the skew and preventing 6 ns runt pulses on the differential line while still meeting 50 Mbps.
When swapping from Avago HCPL-7723 (old DIP-8 thru-hole) to HCPL-7723-560E gull-wing SMD during rewo
Use a 0.125 mm thick stencil with 80 % area aperture for pads 1, 4, 5, 8 (isolation barrier pins) and 90 % for signal pins; this deposits 120 µm paste that reflows to 70 µm standoff, giving enough compliance to absorb 13 ppm/°C difference between FR-4 and the HCPL-7723-560E’s epoxy compound across 1000 -40→85 °C cycles without corner crack failures.
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Sep 15 2026
